View MAX662013_4883866.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-4039; rev 1; 1/13 max6620 quad linear fan-speed controller evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maximintegrated.com. general description the max6620 controls the speeds of up to four fans using four independent linear voltage outputs. the drive voltages for the fans are controlled directly over the i 2 c interface. each output drives the base of an external bipolar transistor or the gate of a fet in high- side drive configuration. voltage feedback at the fan? power-supply terminal is used to force the correct out- put voltage. the max6620 offers two methods for fan control. in rpm mode, the max6620 monitors four fan tachometer logic outputs for precise (?%) control of fan rpm and detection of fan failure. in dac mode, each fan is dri- ven with a voltage resolution of 9 bits and the tachome- ter outputs of the fans are monitored for failure. the dac_start input selects the fan power-supply voltage at startup to ensure appropriate fan drive when power is first applied. a watchdog feature turns the fans fully on to protect the system if there are no valid i 2 c communications within a preset timeout period. the max6620 operates from a 3.0v to 5.5v power sup- ply with low 250? supply current, and the i 2 c-compati- ble interface makes it ideal for fan control in a wide range of cooling applications. the max6620 is avail- able in a 28-pin tqfn package and operates over the -40? to +125? automotive temperature range. applications consumer products servers communications equipment storage equipment features controls up to four independent fans with linear (dc) drive uses four external low-cost pass transistors 1% accuracy precision rpm control controlled voltage rate-of-change for best acoustics i 2 c bus interface 3.0v to 5.5v supply voltage range 250 a (typ) operating supply current 3 a (typ) shutdown supply current small 5mm x 5mm footprint max6620 tqfn (5mm 5mm 0.8mm) top view 26 27 25 24 10 9 11 sda gnd addr dac_start spinup_start 12 scl + dacfb2 gnd dacout3 tach2 dacfb3 tach3 12 gnd 4567 20 21 19 17 16 15 fan vcc dacout4 gnd gnd x2 wd_start dacout2 3 18 28 8 fan_fail x1 dacout1 23 13 dacfb4 dacfb1 22 14 tach4 tach1 pin configuration ordering information + denotes a lead-free package. * ep = exposed paddle. part temp range pin-package max6620ati+ -40? to +125? 28 tqfn-ep* typical application circuit appears at end of data sheet.
max6620 quad linear fan-speed controller 2 maxim integrated absolute maximum ratings electrical characteristics (t a = -40? to +125?, v cc = 3.0v to 5.5v, unless otherwise noted. typical values are at t a = +25?, v cc = 3.3v.) (note 3) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. vcc to gnd ..........................................................-0.3v to +6.0v fan_fail , sda, scl to gnd ...............................-0.3v to +6.0v addr, spinup_start, dac_start, wd_start, x1, x2 to gnd ........................................-0.3v to (v cc + 0.3v) all other pins to gnd..........................................-0.3v to +13.5v input current at dacout_ pins (note 1) ...............+5ma/-50ma input current at any pin (note 1)..........................................5ma esd protection (all pins, human body model) (note 2) ...?000v continuous power dissipation (t a = +70?) 28-pin tqfn (derate 34.5mw/? above +70?) ....2758.6mw operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? soldering temperature (reflow) .......................................+260? lead temperature (soldering, 10s) .................................+300? parameter symbol condition min typ max units operating supply voltage v cc 3.0 5.5 v operating supply current i cc v cc = 5.5v 0.25 0.60 ma i 2 c inactive 0.2 0.5 ma quiescent supply current shutdown mode 3 20 a v fanhi 10 12 13.5 v fan supply voltage v fanlo 4.0 5.0 5.5 v v gnd + 10v < v dacout_ < 11.5v, v fan = 12v -18 dacout_ output current i dacout_ v gnd + 3v < v dacout_ < 10v, v fan = 12v -16 ma dacout_ output voltage v dacout_ i dacout_ = 5ma 0.05 v fan - 0.1 v v fan = v fanhi 256/535 v fan = v fanlo 256/567 v fan = 12v 5.54 5.74 5.94 dac feedback voltage at half scale dac fbhs at dacfb_, code = 0x100, i dacout_ = 5ma v fan = 5v 2.05 2.25 2.45 v v fan = v fanhi 511/535 dac fbfs v fan = v fanlo 511/567 v fan = 12v 11.25 11.45 11.65 dac feedback voltage at full scale v dacfb511 at dacfb_, code = 0x1ff, i dacout_ = 5ma v fan = 5v 4.3 4.5 4.7 v drive voltage resolution 9 bit dacfb_ impedance r dacfb 1m ? tach minimum input pulse width 25 ? internal reference frequency accuracy (note 4) -3 +3 % using 32.768khz crystal -0.1 +0.1 tach count accuracy (note 4) using on-chip oscillator -2 +2 % note 1: absolute maximum ratings indicate limits beyond which damage to the device may occur. dc and ac electrical specifica- tions do not apply when operating the device beyond its rated operating conditions. note 2: human body model, 100pf discharged through a 1.5k ? resistor.
max6620 quad linear fan-speed controller 3 maxim integrated electrical characteristics (continued) (t a = -40? to +125?, v cc = 3.0v to 5.5v, unless otherwise noted. typical values are at t a = +25?, v cc = 3.3v.) (note 3) parameter symbol condition min typ max units using 32.768khz crystal, test at 850rpm -1 +1 fan control accuracy (note 4) using on-chip oscillator -3 +3 % xtal oscillator startup time 2s x1 input threshold 0.7 v v cc 2 por threshold v fan 3.5 v logic (sda, scl, fan_fail , wd_start, tach_) input high voltage v ih v cc x 0.7 v input low voltage v il v cc x 0.3 v input high current i ih 1.0 ? input low current i il -1.0 ? input capacitance all digital inputs 6 pf output high current 100 ? output low voltage i ol = 3ma 0.4 v logic (dac_start, spin_start, addr) input high voltage v ih v cc - 0.5 v input low voltage v il 0.5 v input high current i ih 1.0 ? input low current i il -1.0 ? input capacitance all digital inputs 6 pf i 2 c-compatible timing (notes 5, 6) serial clock frequency f scl 400 khz bus free time between stop and start conditions t buf 1.3 ? start condition hold time t hd:sta 0.6 ? stop condition setup time t su:sto 600 ns clock low period t low 1.3 ? clock high period t high 0.6 ? start condition setup time t su:sta 600 ns data setup time t su:dat 100 ns data out hold time t dh 100 ns data in hold time t hd:dat (note 6) 0 0.9 ? maximum receive scl/sda rise time t r (note 8) 300 ns minimum receive scl/sda rise time t r (note 7) 20 + 0.1 x c b ns
max6620 quad linear fan-speed controller 4 maxim integrated electrical characteristics (continued) (t a = -40? to +125?, v cc = 3.0v to 5.5v, unless otherwise noted. typical values are at t a = +25?, v cc = 3.3v.) (note 3) parameter symbol condition min typ max units maximum receive scl/sda fall time t f 300 ns minimum receive scl/sda fall time t f (note 7) 20 + 0.1 x c b ns transmit sda fall time t f (note 7) 20 + 0.1 x c b 250 ns pulse width of suppressed spike t sp (note 8) 0 50 ns output fall time c l = 400pf, i out = 3ma 250 ns sda time low for reset of serial interface t timeout (note 9) 20 50 ms note 3: all parts will operate properly over the v cc supply voltage range of 3.0v to 5.5v. note 4: guaranteed by design and characterization. note 5: all timing specifications are guaranteed by design. note 6: a master device must provide a hold time of at least 300ns for the sda signal to bridge the undefined region of scl? falling e dge. note 7: c b = total capacitance of one bus line in pf. tested with c b = 400pf. note 8: input filters on sda and scl suppress noise spikes less than 50ns. note 9: holding the sda line low for a time greater than t timeout will cause the devices to reset sda to the idle state of the serial bus communication (sda set high). t hd,sta t high t r t f t hd,sta s sr a scl sda t su,sta t su,sto t r t f t buf t low t su,dat t hd,dat ps figure 1. i 2 c serial interface timing
tach count accuracy with int clk vs. supply voltage max6620 toc01 supply voltage (v) tach count accuracy with int clk (%) 5.0 4.5 3.5 4.0 -1.5 -1.0 -0.5 0 1.0 0.5 1.5 2.0 -2.0 3.0 5.5 v fan = 12v t a = 0 c t a = +25 c t a = +125 c t a = +70 c tach count accuracy with ext clk vs. supply voltage max6620 toc02 supply voltage (v) tach count accuracy with ext clk (%) 5.0 4.5 3.5 4.0 -1.5 -1.0 -0.5 0 1.0 0.5 1.5 2.0 -2.0 3.0 5.5 v fan = 12v t a = 0 c, +70 c, +125 c t a = +25 c tach count accuracy with int clk vs. temperature max6620 toc03 temperature ( c) tach count accuracy with int clk (%) 80 35 -10 -1.5 -1.0 -0.5 0 1.0 0.5 1.5 2.0 -2.0 -55 125 v fan = 12v v cc = 5.0v v cc = 3.3v tach count accuracy with ext clk vs. temperature max6620 toc04 temperature ( c) tach count accuracy with ext clk (%) 80 35 -10 -1.5 -1.0 -0.5 0 1.0 0.5 1.5 2.0 -2.0 -55 125 v fan = 12v v cc = 3.3v, 5.0v dacfb_ voltage accuracy vs. temperature max6620 toc05 temperature ( c) dacfb voltage accuracy (%) 80 35 -10 -1.5 -1.0 -0.5 0 1.0 0.5 1.5 2.0 -2.0 -55 125 v fan = 12v v cc = 3.0v, 3.3v, 5.0v dacfb_ voltage accuracy vs. supply voltage max6620 toc06 supply voltage (v) dacfb voltage accuracy (%) 5.0 4.5 4.0 3.5 -1.5 -1.0 -0.5 0 1.0 0.5 1.5 2.0 -2.0 3.0 5.5 v fan = 12v dacfb_ voltage accuracy vs. output current max6620 toc07 output current (ma) dacfb voltage accuracy (%) 9.0 8.0 7.0 6.0 -1.5 -1.0 -0.5 0 1.0 0.5 1.5 2.0 -2.0 5.0 10.0 8.5 7.5 6.5 5.5 9.5 v fan = 12v v cc = 3.0v, 3.3v v cc = 5.5v standby supply current vs. supply voltage max6620 toc08 supply voltage (v) standby supply current ( a) 5.0 4.5 4.0 3.5 50 100 150 200 250 300 400 350 450 500 0 3.0 5.5 v fan = 12v int clk ext clk operating supply current vs. supply voltage max6620 toc09 supply voltage (v) operating supply current (ma) 5.0 4.5 4.0 3.5 0.1 0.2 0.3 0.5 0.4 0.6 0 3.0 5.5 v fan = 12v int clk ext clk typical operating characteristics (v cc = 3.3v, v fan = 12v, t a = +25?, unless otherwise noted.) max6620 quad linear fan-speed controller 5 maxim integrated
max6620 quad linear fan-speed controller 6 maxim integrated tach count accuracy with int clk vs. supply voltage max6620 toc10 supply voltage (v) tach count accuracy with int clk (%) 5.0 4.5 4.0 3.5 -1.5 -1.0 -0.5 0 1.5 1.0 0.5 2.0 -2.0 3.0 5.5 v fan = 5.0v t a = 0 c t a = +25 c t a = +125 c t a = +70 c tach count accuracy with ext clk vs. supply voltage max6620 toc11 supply voltage (v) tach count accuracy with ext clk (%) 5.0 4.5 4.0 3.5 -1.5 -1.0 -0.5 0 1.5 1.0 0.5 2.0 -2.0 3.0 5.5 v fan = 5.0v t a = 0 c, +70 c, +125 c t a = +25 c tach count accuracy with int clk vs. temperature max6620 toc12 temperature ( c) tach count accuracy with int clk (%) 80 35 -10 -1.5 -1.0 -0.5 0 1.5 1.0 0.5 2.0 -2.0 -55 125 v fan = 5.0v v cc = 3.3v v cc = 5.0v tach count accuracy with ext clk vs. temperature max6620 toc13 temperature ( c) tach count accuracy with ext clk (%) 80 35 -10 -1.5 -1.0 -0.5 0 1.5 1.0 0.5 2.0 -2.0 -55 125 v fan = 5.0v v cc = 3.3v, 5.0v dacfb_ voltage accuracy vs. temperature max6620 toc14 temperature ( c) dacfb voltage accuracy (%) 80 35 -10 -3.5 -2.5 -1.5 0.5 -0.5 3.5 2.5 1.5 4.5 -4.5 -55 125 v fan = 5.0v v cc = 3.0v v cc = 3.3v v cc = 5.5v dacfb_ voltage accuracy vs. supply voltage max6620 toc15 supply voltage (v) dacfb voltage accuracy (%) 5.0 4.5 4.0 3.5 -3.5 -2.5 -1.5 0.5 -0.5 3.5 2.5 1.5 4.5 -4.5 3.0 5.5 v fan = 5.0v dacfb_ voltage accuracy vs. output current max6620 toc16 output current (ma) dacfb voltage accuracy (%) 9.0 8.0 7.0 6.0 -3.5 -2.5 -1.5 0.5 -0.5 3.5 2.5 1.5 4.5 -4.5 5.0 10.0 8.5 7.5 6.5 5.5 9.5 v fan = 5.0v v cc = 3.0v, 3.3v v cc = 5.5v standby supply current vs. supply voltage max6620 toc17 supply voltage (v) standby supply current ( a) 5.0 4.5 4.0 3.5 100 50 150 200 300 250 450 400 350 500 0 3.0 5.5 v fan = 5.0v int clk ext clk operating supply current vs. supply voltage max6620 toc18 supply voltage (v) operating supply current (ma) 5.0 5.5 4.5 4.0 3.5 0.1 0.2 0.3 0.5 0.4 0.6 0 3.0 v fan = 5.0v int clk ext clk typical operating characteristics (continued) (v cc = 3.3v, v fan = 12v, t a = +25?, unless otherwise noted.)
pin description pin name function 1 scl i 2 c serial-clock input. can be pulled up to 5.5v regardless of v cc . open circuit when v cc = 0v. 2 sda open-drain, i 2 c serial-data input/output. can be pulled up to 5.5v regardless of v cc . open circuit when v cc = 0v. 3 wd_start startup watchdog set input. this input is sampled when power is first applied and sets the initial i 2 c watchdog behavior. when connected to gnd, the watchdog function is disabled. when connected to v cc , the max6620 monitors sda. if 10s elapse without a valid i 2 c transaction, the fan drive goes to 100%. 4, 10, 11, 18, 25 gnd ground 5 addr i 2 c address set input. this input is sampled when power is first applied and sets the i 2 c slave address. when connected to gnd, the slave address will be 0x50. when unconnected, the slave address will be 0x52. when connected to v cc , the slave address will be 0x54. 6 dac_start startup fan drive dac set input. this input is sampled when power is first applied and sets the power-up value for the fan drive voltage. when connected to gnd, the fan drive voltage will be 0%. when unconnected, the fan drive voltage will be 75%. when connected to v cc , the fan drive voltage will be 100%. 7s p in u p _s tart startup spin-up set input. this input is sampled when power is first applied and sets the initial spin-up behavior. when connected to gnd, spin-up is disabled. when connected to v cc at power-up, the fan is driven with a full-scale drive voltage until two tachometer pulses have been detected, or 1s has elapsed. when unconnected, the fan is driven with a full-scale drive voltage until two tachometer pulses have been detected, or 0.5s has elapsed. spin-up behavior may be modified by writing appropriate settings to the max6620? registers. 8, 9 x1, x2 crystal oscillator inputs. connections for a standard 32.768khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (c l ) of 12pf. connect an external 32.768khz oscillator across x1 and x2 for operation with the external oscillator. if no crystal or external oscillator is connected, the max6620 will use its internal oscillator. 12, 17, 19, 24 dacout4 dacout1 fan drive dac outputs. connect to the gate of a p-channel mosfet or base of a pnp bipolar transistor. 13, 16, 20, 23 dacfb4 dacfb1 d ac feed b ack inp uts. c onnect a 0.1f cap aci tor b etw een these p i ns and gn d . c onnect to the sup p l y p i n of the fan and to the d r ai n of a p - channel m o s fe t or col l ector of a p n p b i p ol ar tr ansi stor . 14, 15, 21, 22 tach4?ach1 fan tachometer logic inputs. these inputs accept input voltages up to v fan . 26 fan fan power-supply voltage input. connect to the fan power supply (v fan ). bypass with a 0.1? capacitor to gnd. 27 vcc power-supply input. 3.3v nominal. bypass v cc to gnd with a 0.1? capacitor. 28 fan_fail active-low, open-drain fan failure output. active only when fault is present; open-circuit when v cc = 0v. this pin can be pulled up to 5.5v regardless of v cc . ?p exposed paddle. internally connected to gnd. connect to a large ground plane to maximize thermal performance. not intended as an electrical connection point. max6620 quad linear fan-speed controller 7 maxim integrated
max6620 quad linear fan-speed controller 8 maxim integrated write byte format read byte format send byte format receive byte format slave address: equiva- lent to chip-select line of a 3-wire interface command byte: selects which register you are writing to data byte: data goes into the register set by the command byte (to set thresholds, configuration masks, and sampling rate) slave address: equiva- lent to chip-select line command byte: selects which register you are reading from slave address: repeated due to change in data- flow direction data byte: reads from the register set by the command byte command byte: sends com- mand with no data, usually used for one-shot command data byte: reads data from the register commanded by the last read byte or write byte transmission; also used for smbus alert response return address s = start condition shaded = slave transmission p = stop condition a = not acknowledged figure 2. i 2 c protocols s address rd a data a p 7 bits 8 bits wr s a command a p 8 bits address 7 bits p 1 a data 8 bits a command 8 bits a wr address 7 bits s s address wr a command a s address 7 bits 8 bits 7 bits rd a data 8 bits a p detailed description the max6620 controls the speeds of up to four fans using four independent linear voltage outputs. the drive voltages for the fans are controlled directly over the i 2 c interface. each of the outputs (dacout1 dacout4) drive the base of an external pnp or the gate of a p-channel mosfet. voltage feedback at the fan? power-supply terminal is used to force the output voltage. the max6620 monitors fan tachometer logic outputs for precise (1%) control of fan rpm and detection of fan failure. when the max6620 is used with 2-wire fans, these inputs are not used, and the fans can be driven to the desired voltage without using tachometer feed- back. three inputs set the fan drive status on application of power. the dac_start input selects the fan-supply voltage (100%, 75%, or 0%) at startup to ensure appro- priate fan drive when power is first applied. the spin_start input selects whether spin-up will be applied to the fans at power-up. wd_start selects whether lack of i 2 c activity will force the fans to full speed. when the watchdog function is enabled, the fans will be driven to full speed if there is no i 2 c activity for a period of 2s, 6s, or 10s. digital interface the max6620 features an i 2 c-compatible, 2-wire serial interface consisting of a bidirectional serial data line (sda) and a serial clock line (scl). sda and scl facili- tate bidirectional communication between the max6620 and the master at rates up to 400khz. the master (typi- cally a microcontroller) initiates data transfer on the bus and generates scl. sda and scl require 4.7k ? (typ) pullup resistors. bit transfer one data bit is transferred during each scl clock cycle. nine clock cycles are required to transfer the data into or out of the max6620. the data on sda must remain stable during the high period of the scl clock pulse, as changes in sda while scl is high are control signals (see the start and stop conditions section). both sda and scl idle high.
max6620 quad linear fan-speed controller 9 maxim integrated start and stop conditions the master initiates a transmission with a start condi- tion (s), a high-to-low transition on sda with scl high. the master terminates a transmission with a stop condi- tion (p), a low-to-high transition on sda while scl is high (figure 3). the stop condition frees the bus and places all devices in f/s mode (figure 1). use a repeated start condition (sr) in place of a stop condition to leave the bus active and in its current timing mode. acknowledge bits successful data transfers are acknowledged with an acknowledge bit (a) or a not-acknowledge bit ( a ). both the master and the max6620 (slave) generate acknowl- edge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (9th pulse), and keep it low during the high period of the clock pulse (figure 4). to generate a not acknowledge, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves it high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuc- cessful data transfers. an unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the master should reattempt communication at a later time. a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave e = slave pulls smbdata line low f = acknowledge bit clocked into master g = msb of data clocked into slave h = lsb of data clocked into slave i = master pulls data line low j = acknowledge clocked into slave k = acknowledge clock pulse l = stop condition m = new start condition scl ab cd e fg h i j k sda t su:sta t hd:sta t low t high t su:dat t hd:dat t su:sto t buf l m figure 3. i 2 c write timing diagram a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave e = slave pulls smbdata line low f = acknowledge bit clocked into master g = msb of data clocked into master h = lsb of data clocked into master i = master pulls data line low j = acknowledge clocked into slave k = acknowledge clock pulse l = stop condition m = new start condition scl ab cd e fg hij sda t su:sta t hd:sta t low t high t su:dat t su:sto t buf lm k figure 4. i 2 c read timing diagram
max6620 quad linear fan-speed controller 10 maxim integrated slave address a master initiates communication with a slave device by issuing a start condition followed by a slave address byte. as shown in figure 5, the slave address byte con- sists of 7 address bits and a read/write bit (r/ w ). when idle, the max6620 continuously waits for a start con- dition followed by its slave address. the first four bits (msbs) of the slave address have been factory pro- grammed and are always 0101 and the seventh bit is 0 . connect addr to gnd or v cc , or leave it unconnected to program d2 and d1 of the slave address according to table 1. after receiving the address, the max6620 (slave) issues an acknowledgement by pulling sda low for one clock cycle. data byte (read and write) single read and burst read. a single read begins with the bus master issuing a start condition followed by the seven slave id address bits and a zero (wr, figure 2), which is followed by an acknowledge bit (a) from the slave corresponding to the slave id. next, the master sends out an 8-bit register address, which is also followed by an acknowledge bit from the slave. the bus master issues another start condition and the same seven slave id address bits followed by a one (rd, figure 2), with the slave producing an acknowl- edge bit. the slave then sends out the 8-bit data corre- sponding to the register address previously written by the master. the bus master sends back a not-acknowl- edge bit ( a ). this completes the single read process and a stop condition is issued by the bus master. in a burst read, the process is the same as a single read except that the bus master issues an acknowl- edge bit after each byte transmitted by the slave. after each acknowledge bit, the register address increments by one, and the data from the next register is transmit- ted by the slave. the process continues, with data reads followed by acknowledges. after the register with the highest address is read, the register pointer rolls over to point to the first register. to terminate a burst read, the bus master issues a stop condition. single write and burst write. a single write begins with the bus master issuing a start condition followed by the seven slave id address bits and a zero (wr, figure 2), which is followed by an acknowledge bit (a) from the slave corresponding to the slave id. next, the master sends out an 8-bit register address, which is also followed by an acknowledge bit from the slave. after the acknowledge bit, 8-bit data is written to the register, and the slave issues a third acknowledgement. a stop condition is issued by the bus master to com- plete the single write process. in a burst write, the process is similar to a single write except that the master does not issue a stop condition immediately after the first byte has been written. after the first write is completed, the slave issues an acknowledge bit, the register address increments by one, and the data to be written to the next register is transmitted by the master. the process continues, with data writes followed by acknowledges. after the regis- ter with the highest available address is written, the reg- ister pointer rolls over to point to the first register. to terminate a burst write, the bus master issues a stop condition. fan drive the max6620 uses external pass transistors to power the fans. dacout1?acout4 adjust the power- supply voltage for each fan by driving the base of a pnp bipolar transistor, or the gate of a p-mosfet. the resulting fan-supply voltage is fed back to dacfb_. this closes the voltage feedback loop. the system power supply for the output devices is v fan . v fan is slave address addr connection hex binary gnd 0x50 0101 000 unconnected 0x52 0101 010 v cc 0x54 0101 100 table 1. slave address setting with addr pin sda scl 0101 1234 d2 d1 0 r/w 56789 s a acknowledge figure 5. max6620 slave address byte
max6620 quad linear fan-speed controller 11 maxim integrated bit 7? bit 0 ack bit bit 7??it ack bit 8-bit data 8-bit register address 8-bit register address 8-bit register address as bit 7..bit 0 ack bit 7-bit slave id 0 as as s p single write single read burst write burst read bit 7??bit 0 ack bit bit 7.bit 0 ack bit bit 7??it 0 ack bit 8-bit data bit 7.bit 0 ack bit 7-bit slave id 0 as as s 7-bit slave id 1as s p first 8-bit data 8-bit register address bit 7?bit 0 ack bit bit 7?bit 0 ack bit bit 7??it 0 ack bit bit 7??it 0 ack bit as 7-bit slave id 0 as as last 8-bit data as p s bit 7??it 0 ack bit bit 7??it 0 ack bit last 8-bit data bit 7? bit 0 ack bit 7-bit slave id 0 as as 7-bit slave id 1 as first 8-bit data am bit 7??bit 0 ack bit s s p s: 2-wire bus start condition by master p: 2-wire bus stop condition by master as: acknowledge by slave am: acknowledge by master am: no acknowledge by master am am figure 6. read and write summary
max6620 quad linear fan-speed controller 12 maxim integrated nominally 12v or 5v. the drive to the fans is proportion- al to v fan . see the fan_ target drive voltage registers and the applications information sections for more details. fan-speed control dac (voltage) mode. in dac mode, the max6620 sim- ply sets the voltage that powers the fan. the fan? speed is related, but not precisely proportional to, the drive voltage. the drive voltage is set by the fan_ target drive voltage registers and may be read from the fan_ drive voltage registers. because the output voltage can ramp to new values at a controlled rate, the values in the two registers may be different. see the register descriptions and applications information sec- tions for details. rpm mode. in rpm mode, the max6620 monitors tachometer output pulses from the fan and adjusts the fan drive voltage to force the fan? speed to the desired value. fan speed is measured by counting the number of internal 8192hz clock cycles that take place during a selectable number of tachometer periods. the number of clock cycles counted (11-bit value) is stored in the fan_ tach count registers, and the desired number of cycles is stored in the fan_ target tach count regis- ters. see the register descriptions and applications information sections for details. rate-of-change control. sudden changes in fan speed can be easily heard by users. the max6620 helps reduce the audibility of fan-speed changes by controlling the rate at which the drive to the fan is incre- mented. four bits in the fan_ dynamics registers set the rate at which the fan drive voltage is incremented. this allows the time required for a change in fan speed to be varied from 0 (in dac mode only) to several min- utes. see the register descriptions and applications information sections for details. monitoring tachometer signals. the tach_ inputs accept tachometer or ?ocked-rotor?output signals from 3- or 4-wire fans. when measuring fan speed, the max6620 counts the number of internal 8192hz clock cycles that occur during 1, 2, 4, 8, 16, or 32 tachometer periods. the number of tachometer periods is selec- table for each fan by using the appropriate fan_ dynamics register. tachometer pulses <25? in dura- tion are ignored to minimize the effect of noise on the tachometer lines. the tach count for a given rpm can be obtained from the following equation: where: np = number of tachometer pulses per revolution. most general-purpose brushless dc fans produce two tachometer pulses per revolution. sr = 1, 2, 4, 8, 16, or 32. see the fan_ speed range information in the fan_ dynamics register s (06h, 07h, 08h, 09h)?or = 0100 1100 section. the tachometer count consists of 11 bits in the fan_ tach count registers and is available in rpm and dac modes. in rpm mode, the desired fan count is written to the fan_ target tach count registers. fan failure detection when enabled, the max6620 monitors the tach_ inputs to determine when a fan has failed. for fans with tachometer outputs, failure is detected in various ways depending on the fan control mode. in every case, four consecutive fault detections are required to decide whether the fan has failed. in dac mode, the fan_ target tach count registers hold the upper limit for tachometer count values; a fault condition is identified when a tach count exceeds the value written to the fan_ target tach count registers for more than 1s. in rpm mode, a fault condition is identified when any of the following three conditions occur for more than 1s: 1) the tach count exceeds the value of the fan_ target tach count registers while the fan drive voltage is at full-scale, 2) the tach count exceeds two times the fan_ target tach count value, or 3) the tach count reaches its full count of 7ffh. some fans have locked rotor outputs that produce a logic-level output to indicate that the fan has stopped spinning. these signals can be monitored by setting d2:d1 in the fan_ configuration registers. d2 selects locked rotor or tachometer monitoring and d1 selects the polarity of the locked rotor signal. a fan fault has occurred when a locked rotor signal has been present for 1s. fan failure is indicated in the fan fault register and also with the open-drain fan_fail output. the fan_fail output may be masked using the mask bits in the fan fault register. when a fan failure is detected, drive to the affected fan is removed. drive may be restored by writing a new dac or fan count target to the fan? control registers. the global configuration regis- tach count rpm sr np rpm np sr = = 60 8192 491520
max6620 quad linear fan-speed controller 13 maxim integrated ter? bit d4 can be used to cause a fan failure to force the remaining fan speeds to 100%. watchdog the max6620 includes an optional i 2 c watchdog func- tion that monitors the i 2 c bus for transactions. when the watchdog function is enabled, all fans will be forced to full speed if no i 2 c transactions occur within a selected period (2s, 6s, or 10s). spin-up when a fan is not spinning, and a voltage less than the nominal fan-supply voltage is applied to its power- supply terminals, it may fail to start spinning. to over- come this, the full nominal supply voltage may be applied to the fan terminals for a short time before a lower voltage is applied. this ?pin-up?period allows the fan to overcome inertia and begin operating. spin- up is controlled using the fan_ configuration registers. spin-up can be disabled, or it can cause the fan to be driven with the full supply voltage until it produces two tachometer pulses, up to a maximum of 0.5s, 1s, or 2s when the fan is started. por options three inputs allow set up of the max6620? behavior at power-up. these inputs are sampled when power is first applied to the max6620: ? wd_start. connect wd_start to v cc to enable, or to ground to disable, the watchdog function. when enabled using wd_start, the timeout period is 10s. after power is applied, the watchdog function may be enabled or disabled through the global configuration register. ? spinup_start. at power-up, spin-up operation is controlled by the spinup_start pin, which can be connected to ground (spin-up disabled), v cc (spin- up for a maximum of 1s), or unconnected (spin-up for a maximum of 0.5s). ? dac_start. this input controls the fan drive volt- age (for all four fans) at power-up. when connected to ground, the initial fan drive voltage will be 0v. when connected to v cc , the initial fan drive voltage will be full scale. when unconnected, the initial fan drive voltage will be 75% of v fan .
max6620 quad linear fan-speed controller 14 maxim integrated r /w r egist er n o ./a d dr ess po r st a t e f u n c t io n d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r/w 00h 0000 0x x x gl ob al c onfi g ur ati on run: 0 = r un 1 = standby p or: 0 = nor m al 1 = r eset bus timeout (35ms): 0 = enabled 1 = disabled fans to 100% on failure: 0 = enabled 1 = disabled os c : 0 = i nter nal 1 = x tal i 2 c w atchd og : 00 = n o w atchd og 01 = 2s 10 = 6s 11 = 10s i 2 c watchd og s tatus ( r ead onl y) : 1 = el ap sed r/w 01h 0000 1111 fan faul t fan 4 faul t fan 3 faul t fan 2 faul t fan 1 faul t fan 4 mask fan 3 mask fan 2 mask fan 1 mask r/w 02h 0x x 0 0000 fan 1 c onfi g ur ati on m od e: 0 = d ac 1 = rp m s p i n- u p : 00 = n o sp i n- up 01 = tw o tac h counts or 0.5s 10 = tw o tac h counts or 1s 11 = tw o tac h counts or 2s tac h i np ut enab l e tac h / locked rotor : 0 = tac h 1 = l ocked r otor locked rotor p ol ar i ty: 0 = l ow 1 = hi g h r/w 03h 0x x 0 0000 fan 2 c onfi g ur ati on s am e as fan 1 c onfi g ur ati on r/w 04h 0x x 0 0000 fan 3 c onfi g ur ati on s am e as fan 1 c onfi g ur ati on r/w 05h 0x x 0 0000 fan 4 c onfi g ur ati on s am e as fan 1 c onfi g ur ati on r/w 06h 0100 1100 fan 1 d ynam i cs s p eed rang e ( tac h p er i od s) : 000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 32 111 = 32 d ac rate- of- c hang e: 000 = 0s p er ls b ( d ac m od e) 0.0625s p er ls b ( rp m m od e) 001 = 0.015625s p er ls b 010 = 0.03125s p er ls b 011 = 0.0625s p er ls b 100 = 0.125s p er ls b 101 = 0.25s p er ls b 110 = 0.5s p er ls b 111 = 1s p er ls b r/w 07h 0100 1100 fan 2 d ynam i cs s am e as fan 1 d ynam i cs r/w 08h 0100 1100 fan 3 d ynam i cs s am e as fan 1 d ynam i cs r/w 09h 0100 1100 fan 4 d ynam i cs s am e as fan 1 d ynam i cs register map registers
max6620 quad linear fan-speed controller 15 maxim integrated r /w r eg ist er n o . /a d d r ess po r st a t e f u n c t io n d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10h 1111 1111 d 10 d 9d 8d 7d 6d 5d 4d 3 r 11h 1110 0000 fan 1 tac h c ount d 2d 1d 0 12h 1111 1111 r 13h 1110 0000 fan 2 tac h c ount s am e as fan 1 tac h c ount 14h 1111 1111 r 15h 1110 0000 fan 3 tac h c ount s am e as fan 1 tac h c ount 16h 1111 1111 r 17h 1110 0000 fan 4 tac h c ount s am e as fan 1 tac h c ount 18h 0000 0000 d 8d 7d 6d 5d 4d 3d 2d 1 r 19h 0000 0000 fan 1 d r i ve v ol tag e d 0ful l 1ah 0000 0000 r 1bh 0000 0000 fan 2 d r i ve v ol tag e s am e as fan 1 d r i ve v ol tag e 1c h 0000 0000 r 1d h 0000 0000 fan 3 d r i ve v ol tag e s am e as fan 1 d r i ve v ol tag e 1e h 0000 0000 r 1fh 0000 0000 fan 4 d r i ve v ol tag e s am e as fan 1 d r i ve v ol tag e 20h 0011 1100 d 10 d 9d 8d 7d 6d 5d 4d 3 r/w 21h 0000 0000 fan 1 tar g et tac h c ount d 2d 1d 0 22h 0011 1100 r/w 23h 0000 0000 fan 2 tar g et tac h c ount s am e as fan 1 tar g et tac h c ount 24h 0011 1100 r/w 25h 0000 0000 fan 3 tar g et tac h c ount s am e as fan 1 tar g et tac h c ount 26h 0011 1100 r/w 27h 0000 0000 fan 4 tar g et tac h c ount s am e as fan 1 tar g et tac h c ount 28h x x x x x x x x d 8d 7d 6d 5d 4d 3d 2d 1 r/w 29h x 000 0000 fan 1 tar g et d r i ve v ol tag e d 0 2ah x x x x x x x x r/w 2bh x 000 0000 fan 2 tar g et d r i ve v ol tag e s am e as fan 1 tar g et d r i ve v ol tag e 2c hx x x x x x x x r/w 2d hx 000 0000 fan 3 tar g et d r i ve v ol tag e s am e as fan 1 tar g et d r i ve v ol tag e 2e hx x x x x x x x r/w 2fh x 000 0000 fan 4 tar g et d r i ve v ol tag e s am e as fan 1 tar g et d r i ve v ol tag e x = depends on input states at power-up. register map (continued)
max6620 quad linear fan-speed controller 16 maxim integrated global configuration register (00h)?or = 0000 0xxx register descriptions bit r/w function 7 r/w run: 0 = run 1 = standby 6 r/w por: 0 = normal operation 1 = reset all registers to por values this bit automatically resets itself and will always return a 0 when read. 5 r/w i 2 c bus timeout: 0 = enabled 1 = disabled the i 2 c interface will reset if sda is low for more than 35ms. 4 r/w fans to 100% on failure: 0 = if a fan failure is detected, all other fan channels immediately go to full-scale drive voltage to ensure adequate cooling 1 = disabled 3 r/w oscillator selection: selects on-chip oscillator or 32.768khz crystal/ceramic resonator. use crystal if 1% rpm accuracy is required. 0 = internal oscillator (default at power-on) 1 = external 32.768khz crystal when switching from the internal oscillator to an external crystal, the max6620 operates from the internal oscillator until the crystal oscillator has started up. if the crystal is damaged or the oscillator fails to start, the max6620 will continue to operate from the internal oscillator.
max6620 quad linear fan-speed controller 17 maxim integrated global configuration register (00h)?or = 0000 0xxx (continued) bit r/w function 2 1 r/w i 2 c watchdog: when active, the watchdog monitors sda and scl for valid i 2 c transactions. if there are no valid transactions between the master and the max6620 within the watchdog period, all fan output voltages will go to full-scale drive voltage. if the watchdog times out and valid i 2 c transactions begin to occur again, operation will resume with the previous dac value. the master can then program the output voltages, target tach counts, or other functions in the normal manner. when the watchdog function is active, ensure that the master communicates to the max6620 periodically, for example reading a status register. the por state is set by the state of the wd_start pin at power-up. d2:d1 i 2 c watchdog period (s) por condition 00 inactive (no watchdog) wd_start = gnd 01 2 ? 10 6 ? 11 10 wd_start = v cc 0 r i 2 c watchdog status: 0 = i 2 c transactions occurred within watchdog period 1 = time between i 2 c transaction exceeds watchdog period this bit is cleared by i 2 c read from this register.
max6620 quad linear fan-speed controller 18 maxim integrated fan fault register (01h)?or = 0000 1111 bit r/w function 7 r fan 4 fault status: indicates which fans have had faults detected. when a fan fault is detected, the drive to the fan is disabled and the corresponding fault bit is set. the fault bits latch until they are cleared by reading, thus allowing short-term faults to be identified. after a fault status bit is cleared by reading, the corresponding output voltage will remain zero until a fan_ target drive voltage register or fan_ target tach register is written. writing a new target drive voltage or target tach count will cause drive to be applied to the fan again, at which time a new failure-detection cycle will begin. fault conditions are: mode fan_ drive voltage register condition time (s) tach count exceeds value of fan_ target tach count dac any locked rotor asserts >1 1ffh (full) tach count exceeds value of fan_ target tach count tach count exceeds two times of fan_ target tach count value rpm <1ffh tach count reaches it full count of 7ffh >1 fan_fail will be asserted when four consecutive faults are detected. 6 r fan 3 fault status 5 r fan 2 fault status 4 r fan 1 fault status 3 r/w fan 4 fault mask: masks faults on selected fans from asserting the fan_fail output. faults will still be indicated by the fault status bits: 0 = not masked 1 = masked 2 r/w fan 3 fault mask 1 r/w fan 2 fault mask 0 r/w fan 1 fault mask
max6620 quad linear fan-speed controller 19 maxim integrated fan_ configuration registers (02h, 03h, 04h, 05h)?or = 0xx0 0000 bit r/w function 7 r/w rpm/dac: 0 = dac mode. the fan drive voltage is set by the value in the fan_ target drive voltage register. 1 = rpm mode. the fan drive voltage is adjusted to produce the tach count value in the fan_ target tach count register. when changing from dac to rpm mode, if the current rpm value is different from the value selected in the fan_ target tach count register, the drive voltage will start from the current value and increment/ decrement toward the desired value at the selected dac rate-of-change. 6 r/w 5 r/w spin-up: when the fan drive voltage increases from 0v to a value less than the full-scale drive voltage, it may be necessary to drive the fan with the full-scale drive voltage for a brief period to ensure that the fan is spinning before reducing the drive to the selected value. when spin-up is selected, the fan is driven at the full-scale drive voltage until two tachometer pulses have been detected or locked rotor has been cleared. a maximum spin-up time is also selectable to ensure that the spin-up time is not excessive. after two tachometer pulses have been detected, or locked rotor has been cleared or the spin-up has timed out, the drive voltage goes to the value in the fan_ target drive voltage register. the por state is set by the state of the spinup_start pin at power-up. d6:d5 function por condition 00 no spin-up spin_start pin = ground 01 spin-up until two tachometer pulses or clearing of locked rotor, or 0.5s (max) spin_start pin = open 10 spin-up until two tachometer pulses or clearing of locked rotor, or 1s (max) spin_start pin = v cc 11 spin-up until two tachometer pulses or clearing of locked rotor, or 2s (max) ? 4 reserved 3 r/w tach i nput enable: enables tach input function and fan fault detection (automatically enabled in rpm mode). 0 = disabled. when disabled and tach input is not used, bit 1 and bit 2 are ignored. 1 = enabled 2 r/w tach/locked rotor: selects tach input function as tach count or locked rotor. in locked rotor mode, the tach count stops and assertion of the tach input indicates that the fan has stopped. 0 = tach count 1 = locked rotor 1 r/w locked rotor polarity: 0 = low locked rotor. tach input low in locked rotor mode indicates fan is stopped. 1 = high locked rotor. tach input high in locked rotor mode indicates fan is stopped. 0 ? reserved
max6620 quad linear fan-speed controller 20 maxim integrated bit r/w function 7 r/w 6 r/w 5 r/w fan_ speed range: the max6620 determines fan speed by counting the number of internal 8192hz clock cycles (using an 11-bit counter) during one or more fan tachometer periods. three bits set the nominal rpm range for the fan, as shown in the table below. as an example, a setting of 010 causes the max6620 to count the number of 8192hz clock cycles that occur during four complete tachometer periods. if the fan has a nominal speed of 2000rpm and two tachometer pulses per revolution, one tachometer period will be nominally 15ms, and four tachometer periods will be 60ms. with an 8192hz clock, the tach count will therefore be equal to 491. with a fan speed of 1/3 the nominal value, the count will be 1474. if the fan?s nominal speed is 1000rpm, the full-speed tach count will be 983. at 1/3 the nominal speed, there will be 2948 clock cycles in four tachometer periods. this is greater than the maximum 11-bit count of 2047, so four tachometer periods is too many for this fan; a setting of 001 (two clock cycles) is recommended instead. the table below shows the full-speed tachometer counts for several combinations of nominal fan speeds and d7:d5 settings. the shaded combinations will provide the best results. when setting d7:d5, the goal is to obtain the highest tachometer count without exceeding the maximum count of 2047 when the fan is at the minimum speed of interest. for example, if the minimum speed of interest is 1/3 of full speed, the maximum tachometer count will be three times the value shown in the table below: tachometer counts/(counting period) ( 8192hz clock used): rpm d7:d5 number of tach periods counted 500 1000 2000 4000 8000 16000 000 1 491 (60ms) 245 (30ms) 122 (15ms) 61 (7.5ms) 30 (3.75ms) 15 (1.875ms) 001 2 983 (120ms) 491 (60ms) 245 (30ms) 122 (15ms) 61 (7.5ms) 30 (3.75ms) 010 4 1966 (240ms) 983 (120ms) 491 (60ms) 245 (30ms) 122 (15ms) 61 (7.5ms 011 8 2047 (480ms) 1966 (240ms) 983 (120ms) 491 (60ms) 245 (30ms) 122 (15ms) 100 16 2047 (960ms) 2047 (480ms) 1966 (240ms) 983 (120ms 491 (60ms) 245 (30ms) 101, 110, 111 32 2047 (1920ms) 2047 (960ms) 2047 (480ms) 1966 (240ms) 983 (120ms) 491 (60ms) fan_ dynamics registers (06h, 07h, 08h, 09h)?or = 0100 1100
max6620 quad linear fan-speed controller 21 maxim integrated fan_ dynamics registers (06h, 07h, 08h, 09h)?or = 0100 1100 (continued) bit r/w function 4 r/w 3 r/w 2 r/w fan_ dac rate-of-change: the fan drive voltage (at the dacfb_ inputs) varies from 0 to full scale in 512 increments. the rate-of- change bits determine the time interval between output voltage increments/decrements. in rpm mode, a setting of 0 would result in an unstable feedback loop, so a default value of 0.0625 is in effect when 0 is selected. regardless of the settings, there are a few cases for which the rate-of-change is always 0: ? when a target tach count of 2047 (7ffh) is selected, the fan drive voltage immediately goes to 0v. a full-scale target count is assumed to mean that the intent is to shut down the fan, and going directly to 0 drive avoids the possibility of loss of control-loop feedback at high tach counts. if a slow- speed decrease toward 0 is desired, a target tach count at the slowest practical value for the fan should be chosen. o nce that count has been reached, selecting a count of 2047 (7ffh) will then take the drive immediately to 0v. ? when a target fan drive voltage of 0v is selected, the drive voltage immediately goes to 0v. again, it is assumed that the intent is to shut down the fan. if a slow-speed decrease toward 0 is desired, a target fan drive voltage of the slowest practical value for the fan in question should be chosen. once that drive voltage has been reached, selecting a target value of 0 will then take the drive immediately to 0v. ? when the current drive level is 0 in dac mode, selecting a new target fan drive voltage will immediately take the voltage to that value. the fan will spin-up first if spin-up is enabled. ? when the current drive level is 0 in rpm mode, selecting a new target tach count that is less than 2047 (7ffh) will immediately take the drive voltage to the value in the fan_ target drive voltage register. from this value, the drive voltage will increment as needed to achieve the desired tach count. the fan will spin-up first if spin-up is enabled. time between output voltage increments (s) d4:d2 dac mode rpm mode time from 33% to 100% (s) 000 0 0.0625 0 001 0.015625 10 010 0.03125 20 011 0.0625 (default) 40 100 0.125 80 101 0.25 160 110 0.5 320 111 1.0 640 1 ? reserved 0 ? reserved
max6620 quad linear fan-speed controller 22 maxim integrated fan_ tach count registers (10h, 12h, 14h, 16h)?or = 1111 1111 bit r/w function 7 6 5 4 3 2 1 0 r fan_ tach count d10:d3: indicates the number of 8192hz clock pulses counted during the counting period. the fan_ tach count consists of 11 bits contained in two bytes. to minimize noise from spurious tachometer transitions, pulses less than 25? are ignored. fan_ tach count registers (11h, 13h, 15h, 17h)?or = 1110 0000 bit r/w function 7 6 5 r fan_ tach count d7:d5 bit r/w function 7 6 5 4 3 2 1 0 r fan_ drive voltage d8:d1: this is a 9-bit value that ranges from 0 to 511. this register shows the actual fan drive voltage. when the value in this register is 480v, the nominal fan drive voltage of v fan is supplied to the fan, as shown in the table in the fan_ target drive voltage registers section. bit r/w function 7r fan_ drive voltage d0 0r full-scale status: 0 = dac is driving with value of d8:d0 that is not at full scale 1 = dac is driving with full scale voltage fan_ drive voltage registers (18h, 1ah, 1ch, 1eh)?or = 0000 0000 fan_ drive voltage registers (19h, 1bh, 1dh, 1fh)?or = 0000 0000
max6620 quad linear fan-speed controller 23 maxim integrated bit r/w function 7 6 5 4 3 2 1 0 r/w fan_ target tach count d10:d3: in rpm mode, write the desired tachometer count to this register. the max6620 will then adjust the fan drive voltage to achieve this tachometer count. in dac mode, this register has no effect. when changing from dac mode to rpm mode, best results are obtained by loading this register with the desired tach count before changing to rpm mode. the target tach count for a given rpm will be obtained by the following equation: where: np = number of tach pulses per revolution sr = 1, 2, 4, 8, 16, or 32 (see the fan_ speed range information in the fan_ dynamics register s (06h, 07h, 08h, 09h)?or = 0100 1100 section) bit r/w function 7 6 5 r fan_ target tach count d2:d0 fan_ target tach count registers (21h, 23h, 25h, 27h)?or = 0000 0000 fan_ target tach count registers (20h, 22h, 24h, 26h)?or = 0011 1100 the fan_ target tach count consists of 11 bits con- tained in two bytes. the two bytes must be written in order in one or two i 2 c transactions, with no other i 2 c writes in between. these target registers are updated internally at the same time when a second byte (lsb) is written. targettach rpm = 60 8192 np sr
max6620 quad linear fan-speed controller 24 maxim integrated the fan_ target drive voltage consists of 9 bits con- tained in two bytes. the two bytes must be written in order in one or two i 2 c transactions with no other i 2 c writes in between. these target registers are updated internally at the same time when a second byte (lsb) is written. bit r/w function 7 6 5 4 3 2 1 0 r/w fan_ target drive voltage d8:d1: this is a 9-bit value that ranges from 0 to 511 and is contained in two bytes. in dac mode, write the desired fan drive voltage to these two registers. the max6620 will then ramp the fan drive voltage to this value at a rate determined by the dac rate-of-change bits. in rpm mode, the value contained in this register will be the voltage applied to the fan immediately after spin-up or after changing the fan_ target tach count from 2047 (7ffh) to a value lower than 2047 (7ffh). for example, if the fan is currently stopped with spin-up disabled, and a new fan_ target tach count corresponding to 60% of the full-scale fan speed is to be selected, the fan voltage can be programmed to immediately go to 60% of the full-scale drive voltage when the new fan_ target tach count is selected from 2047 (7ffh), and then close the rpm control loop starting from that voltage. the register value is converted to the drive voltage at the fan (or voltage at dacfb_) as follows: d8:d0 fan_ drive voltage (v) decimal hex 5v range 12v range 0 000h 0.000 0.000 200 0c8h 1.764 4.486 300 12ch 2.646 6.729 400 190h 3.527 8.972 480 1e0h 4.232 10.766 511 1ffh 4.506 11.462 the value of the fan_ target drive voltage at por depends on state of the dac_start pin, as shown below: d8:d0 decimal hex dac_start 0 000h gnd 384 180h open 511 1ffh vcc bit r/w function 7r fan_ target drive voltage d0 fan_ target drive voltage registers (29h, 2bh, 2dh, 2fh)?or = x000 0000 fan_ target drive voltage registers (28h, 2ah, 2ch, 2eh)?or = xxxx xxxx
max6620 quad linear fan-speed controller 25 maxim integrated applications information external pass transistors match external pass transistors to the fans being used. ensure that the pass transistor is capable of handling the maximum fan current. for best results, the pass transistor? maximum current rating should be at least 50% greater than the fan? nominal supply current. the transistor should also be capable of dissipating the worst-case power, which usually occurs when the fan is being driven to approximately 50% of the nominal sup- ply voltage. the maximum power dissipation will depend on the thermal resistance of the transistor, its case, and the printed-circuit board (pcb) to which it is soldered. for example, if the worst-case transistor power dissipation occurs when the fan current is 100ma, and the voltage across the fan is 6.5v, the maximum power dissipation will be 650mw. a bcp69t1-d in a sot223-4 package is rated at 1.5w at 25? (about 1w at 70?) when soldered to a 0.93in 2 (6cm 2 ) copper pcb pad, and can easily handle this power dissipation. larger copper pads, packages with lower thermal resistance, or different transistors can give significantly different results. the max6620 uses an advanced output driver design that eliminates the large external capacitors often con- nected across the fan? power-supply terminals. for stability with a variety of fans, connect a 0.1? capaci- tor from dacfb_ to ground. using a low-dropout voltage regulator (ldo) as the pass device voltage regulators can be used instead of discrete tran- sistors to drive the fans (figure 7). the voltage feed- back loop is closed around the regulator to provide the desired output voltage. when using a voltage regulator, note the following: ? most regulators require relatively large capacitors at their inputs and outputs for stability. ? most regulators have a lower output voltage limit that is >0v. if removing the drive from the fan is neces- sary when using a regulator, choose a regulator that has an on/off control input and drive that input from the system microcontroller. fan-speed control (dac and rpm modes) the max6620 has two main modes for controlling fan speeds. in dac mode, the max6620 produces an out- put voltage that drives the fan. this voltage is propor- tional to the main fan power-supply voltage (v fan ). write the 9-bit desired voltage value in the fan_ target drive voltage register. in rpm mode, the max6620 monitors the tachometer signals from the fans through the tach_ inputs and adjusts the drive voltage to yield the desire tachometer count. the tachometer count is the number of internal 8192 clock cycles that are counted during the selected number of tachometer pulses. controlling 2-wire fans (dac mode) in dac mode, the max6620 sets the fan? supply volt- age to the value selected in the fan_ target drive voltage register. tachometer monitoring is never done when controlling a 2-wire fan, so the tach input enable bit in the fan_ configuration register should be set to 0. enabling the tach input when using a 2-wire fan will result in an erroneous fan failure detection. initial settings: ? begin with the por settings. the por value of the fan_ dac rate-of-change bits (4:2 of the fan_ dynamics register) can yield slower fan speed changes than desired. if this is the case, choose a faster value, such as 001. starting the fan: ? write the desired drive voltage value to the fan_ target drive voltage register. changing speeds: ? write the new desired drive voltage value to the fan_ target drive voltage register. stopping the fan: ? write a voltage value of 0 to the fan_ target drive voltage register. controlling 3-wire fans (dac mode) in dac mode, the max6620 sets the fan? supply volt- age to the value selected in the fan_ target drive voltage register. 3-wire fans with tachometer outputs allow monitoring of the fan? speed to detect fan failure. to monitor a fan? speed, the tach input should be enabled.
max6620 quad linear fan-speed controller 26 maxim integrated i 2 c interface, registers, and control logic dac output driver tach monitor 0.1 f v cc 3.0v to 5.5v fan_fail 0.1 f v fan +12v sda scl to i 2 c master v cc dac_start addr spinup_start x1 wd_start x2 (optional crystal) v fan v fan fan2 dacout2 dacfb2 tach2 0.33 f 47 f 2.4k ? 27k ? 470 ? pq20rx v adj v o v in v c v fan +12v v fan fan1 dacout1 dacfb1 tach1 0.33 f 47 f 2.4k ? 27k ? 470 ? pq20rx v adj v o v in v c v fan v fan fan3 dacout4 dacfb4 tach4 0.33 f 47 f 2.4k ? 27k ? 470 ? pq20rx v adj v o v in v c v fan v fan fan3 dacout3 dacfb3 tach3 0.33 f 47 f 2.4k ? 27k ? 470 ? pq20rx v adj v o v in v c figure 7. using low dropout voltage regulators instead of discrete transistors as the pass devices
max6620 quad linear fan-speed controller 27 maxim integrated initial settings: ? begin with the por settings. the por value of the fan_ dac rate-of-change bits (4:2 of the fan_ dynamics register) can yield slower fan speed changes than desired. if this is the case, choose a faster value, such as 001. ? write the desired number of tachometer periods to be counted in the speed range bits (7:5 of the fan_ dynamics register). ? write the maximum allowable tachometer count to the fan_ target tach count registers. tachometer counts greater than this value will result in a fan fault detection. choose a value that will not be encoun- tered during normal operation, accounting for normal fan speed tolerances. note: setting a full-scale target count (2047) will result in the fan drive going to 0v. ? set the tach input enable bit in the fan_ configuration register to 1. note: this bit can be set after the fan has been start- ed, if desired. if the bit is set before writing a target fan drive voltage, the target drive voltage should be set immediately after enabling the tach input to avoid failure detection before the fan has started spinning. starting the fan: ? write the desired drive voltage value to the fan_ target drive voltage register. changing speeds: ? write the new desired drive voltage value to the fan_ target drive voltage register. stopping the fan: ? write a 0 to the tach input enable bit in the fan_ configuration register. this prevents the max6620 from deciding that the fan has failed after it has stopped. ? write a voltage value of 0v to the fan_ target drive voltage register. ? if a gradual decrease in fan speed is desired, write the lowest drive voltage at which the fan will reliably operate. when the drive voltage reaches that value, write 0v to the fan_ target drive voltage register. controlling 3-wire fans (rpm mode) begin as in dac mode and start the fan. changing from dac mode to rpm mode: ? write the desired tachometer count to the fan_ tach count registers. ? set bit 7 of the fan_ configuration register to 1. this selects rpm mode. the fan will go to the selected speed. note: when the dac rate-of-change is set to one of the faster values, the fan drive voltage can, depend- ing on the fan? characteristics, undergo a slow oscil- lation. while this rarely has an audible impact, it can be reduced or eliminated by selecting a slower rate- of-change once the fan? speed has reached or approached its target value. changing speeds: ? write the desired tachometer count to the fan_ target tach count registers. stopping the fan: ? write the current drive voltage into the fan_ target drive voltage register. ? write a value greater than the current tachometer count into the fan_ target tach count register. ? write a 0 to bit 7 of the fan_ configuration register. this selects dac mode. ? write a 0 to the tach input enable bit in the fan_ configuration register. this prevents the max6620 from detecting a high tach count and determining that the fan has failed. ? write a voltage value of 0v to the fan_ target drive voltage register. ? if a gradual decrease in fan speed is desired, write the lowest drive voltage at which the fan will reliably operate. when the drive voltage reaches that value, write 0 to the fan_ target drive voltage register.
max6620 quad linear fan-speed controller 28 maxim integrated i 2 c interface, registers, and control logic dac output driver tach monitor 0.1 f v cc fan_fail 0.1 f v fan sda scl to i 2 c master v cc dac_start addr spinup_start x1 gnd wd_start x2 (optional crystal) v fan fan2 dacout2 dacfb2 tach2 0.1 f 0.1 f 4.7k ? 4.7k ? v fan fan1 dacout1 dacfb1 tach1 0.1 f 0.1 f 4.7k ? 4.7k ? v fan fan4 dacout4 dacfb4 tach4 0.1 f 0.1 f 4.7k ? 4.7k ? v fan fan3 dacout3 dacfb3 tach3 0.1 f 0.1 f 4.7k ? 4.7k ? typical application circuit
max6620 quad linear fan-speed controller 29 maxim integrated chip information process: cmos package information for the latest package outline information and land patterns (foot- prints), go to www.maximintegrated.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 28 tqfn t2855+8 21-0140 90-0028
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integr ated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time . the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 30 ________________________________ maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products , inc. max6620 quad linear fan-speed controller revision number revision date description pages changed 0 3/08 initial release 1 1/13 corrected fan_ dynamics register typos and hex values; added soldering temp; updated package info 12, 18, 20, 21, 24, 29 revision history

▲Up To Search▲

Price & Availability of MAX662013

	To Download MAX662013 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .